IC 74173 DATASHEET PDF

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The 3-state outputs allow the. During 3—state operation, these outputs assume a high— impedance state.

During 3—state operation, these outputs assume a high—. The data outputs change state on the positive going edge of the clock. Enable Controls are low, data at the D inputs are loaded into. The outputs are placed in the 3-stage mode when either of the. When either datasheft both of the Output Enable Controls are high, the Q outputs of the device are in the datasyeet state.

When both controls are low, the device outputs display the data in the flip—flops.

If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs. Output Enable Control inputs.

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(PDF) 74173 Datasheet download

Output Enable Controls are high, the Q outputs of the device. When either M or N or both is are high the output is disabled to the high-impedance state.

When both Data Enable Controls are low, data at the D inputs are loaded into the flip—flops with the rising edge of the Clock input. Data on these pins, when enabled by the. If either of the 2 input disables are taken to a logic high level, the Q outputs are fed back to the inputs, forcing the flip-flops to remain in the same state.

During normal operation of the device, the outputs of the D flip—flops appear at these pins. When either or both of the. A high level on this pin resets all flip—flops and forces the Q outputs low, if they are not already in high—impedance state.

The four D type Flip-Flops operate synchronously from a common clock. When either or both of these controls adtasheet high, there is no change in the state of the flip—flops, regardless of any changes at the D or Clock inputs.

Home – IC Supply – Link.

Data—Enable Controls, are entered into the flip—flops on the. Home – IC Supply – Link. The outputs are placed in the 3-stage mode when either of the output disable pins are in the logic high level.

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During normal operation of the. The input disable allows the flip-flops to remain in their present states without having to disrupt the clock. When either M or N or both is are high the output is disabled to the high-impedance state; however sequential operation of the flip-flops is not affected.

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Clearing is enabled by taking the clear input to a logic high level. A high level on this pin resets all. Active—low Data Enable Control inputs. When both controls are.

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The 3-state outputs allow the device to be used in bus organized systems. Data on these pins, when enabled by the Data—Enable Controls, are entered into the flip—flops on the rising edge of the clock.

Clearing is enabled by taking the clear input to a logic.